/*
 * Memory Setup stuff - taken from blob memsetup.S
 *
 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
 *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
 *
 * Modified for the Samsung SMDK2410 by
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */


#include <config.h>
#include <version.h>


/* some parameters for the board */

/*
 *
 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
 *
 * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
 *
 */

#define BWSCON	0x48000000

/* BWSCON */
#define DW8			(0x0)
#define DW16			(0x1)
#define DW32			(0x2)
#define WAIT			(0x1<<2)
#define UBLB			(0x1<<3)

#define B1_BWSCON		(DW32)
#define B2_BWSCON		(DW16)
#define B3_BWSCON		(DW16 + WAIT + UBLB)
#define B4_BWSCON		(DW16)
#define B5_BWSCON		(DW16)
#define B6_BWSCON		(DW32)
#define B7_BWSCON		(DW32)

/* BANK0CON */
#define B0_Tacs			0x0	/*  0clk */
#define B0_Tcos			0x0	/*  0clk */
#define B0_Tacc			0x7	/* 14clk */
#define B0_Tcoh			0x0	/*  0clk */
#define B0_Tah			0x0	/*  0clk */
#define B0_Tacp			0x0
#define B0_PMC			0x0	/* normal */

/* BANK1CON */
#define B1_Tacs			0x0	/*  0clk */
#define B1_Tcos			0x0	/*  0clk */
#define B1_Tacc			0x7	/* 14clk */
#define B1_Tcoh			0x0	/*  0clk */
#define B1_Tah			0x0	/*  0clk */
#define B1_Tacp			0x0
#define B1_PMC			0x0

#define B2_Tacs			0x0
#define B2_Tcos			0x0
#define B2_Tacc			0x7
#define B2_Tcoh			0x0
#define B2_Tah			0x0
#define B2_Tacp			0x0
#define B2_PMC			0x0

#define B3_Tacs			0x0	/*  0clk */
#define B3_Tcos			0x3	/*  4clk */
#define B3_Tacc			0x7	/* 14clk */
#define B3_Tcoh			0x1	/*  1clk */
#define B3_Tah			0x0	/*  0clk */
#define B3_Tacp			0x3     /*  6clk */
#define B3_PMC			0x0	/* normal */

#define B4_Tacs			0x0	/*  0clk */
#define B4_Tcos			0x0	/*  0clk */
#define B4_Tacc			0x7	/* 14clk */
#define B4_Tcoh			0x0	/*  0clk */
#define B4_Tah			0x0	/*  0clk */
#define B4_Tacp			0x0
#define B4_PMC			0x0	/* normal */

#define B5_Tacs			0x0	/*  0clk */
#define B5_Tcos			0x0	/*  0clk */
#define B5_Tacc			0x7	/* 14clk */
#define B5_Tcoh			0x0	/*  0clk */
#define B5_Tah			0x0	/*  0clk */
#define B5_Tacp			0x0
#define B5_PMC			0x0	/* normal */

#define B6_MT			0x3	/* SDRAM */
#define B6_Trcd			0x1
#define B6_SCAN			0x1	/* 9bit */

#define B7_MT			0x3	/* SDRAM */
#define B7_Trcd			0x1	/* 3clk */
#define B7_SCAN			0x1	/* 9bit */

/* REFRESH parameter */
#define REFEN			0x1	/* Refresh enable */
#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
#if 0
#define Trp			0x0	/* 2clk */
#endif
#define Trc			0x3	/* 7clk */
#define Tchr			0x2	/* 3clk */
#if 0
#define REFCNT			0x4f4 /*1113*/	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
#endif
/**************************************/

#if defined(CONFIG_S3C2440)  
#define Trp         0x2 /* 4clk */  
#define REFCNT          1012  
#else  
#define Trp         0x0 /* 2clk */  
#define REFCNT                  0x0459  
#endif  
/**************************************/  
  
#define S3C24X0_INTERRUPT_BASE      0x4A000000  
#define S3C24X0_CLOCK_POWER_BASE    0x4C000000  
#define S3C2410_NAND_BASE           0x4E000000  
#define S3C24X0_WATCHDOG_BASE       0x53000000  
#define S3C24X0_GPIO_BASE           0x56000000  
#define GPBCON                      0x56000010  
#define GPBDAT                      0x56000014  
#define GPBUP                       0x56000018  
  
#define INTMSK_OFFSET               0x08  
#define INTSUBMSK_OFFSET            0x1c  
#define MPLLCON_OFFSET              0x04  
#define CLKDIVN_OFFSET              0x14  
#define NFCONF_OFFSET               0x00  
#define NFCONT_OFFSET               0x04  
#define NFCMD_OFFSET                0x08  
#define NFSTAT_OFFSET               0x20  
  
#define MDIV_405                    0x7f << 12  
#define PSDIV_405                   0x21          
#define MDIV_200                    0xa1 << 12   
#define PSDIV_200                   0x31 

.globl lowlevel_init
lowlevel_init:  
    /****** Disable Watchdog ******/  
    ldr r0, =S3C24X0_WATCHDOG_BASE  
    mov r1, #0  
    str r1, [r0]  
  
    /****** Disable interrupt by mask all IRQ mask ******/  
    ldr r0, =S3C24X0_INTERRUPT_BASE  
    mvn r1, #0x0  
    str r1, [r0, #INTMSK_OFFSET]  
    str r1, [r0, #INTSUBMSK_OFFSET]  
  
    /****** Initialize System Clock, FCLK:HCLK:PCLK = 1:4:8,default FCLK is 120MHz ******/  
    ldr r0, =S3C24X0_CLOCK_POWER_BASE  
    mov r1, #5  
    str r1, [r0, #CLKDIVN_OFFSET]  
      
    mrc p15, 0, r1, c1, c0, 0  
    orr r1, r1, #0xc0000000  
    mcr p15, 0, r1, c1, c0, 0  
  
    mov r2, #MDIV_405  
    add r2, r2, #PSDIV_405  
    str r2, [r0, #MPLLCON_OFFSET]  
  
   /***** Initialize Nandflash controller ******/  
    mov r1, #S3C2410_NAND_BASE  
    ldr r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) )  
    str r2, [r1, #NFCONF_OFFSET]  
  
    ldr r2, =( (1<<4)|(0<<1)|(1<<0) )   @ Active low CE Control  
    str r2, [r1, #NFCONT_OFFSET]  
      
    ldr r2, =(0x6)                      @ RnB Clear  
    str r2, [r1, #NFSTAT_OFFSET]  
  
    mov r2, #0xff                       @ Reset Nandflash  
    strb    r2, [r1, #NFCMD_OFFSET]  
      
    mov r3, #0       @ Delay for a while  
delay:  
    add r3, r3, #0x1  
    cmp r3, #0xa  
    blt delay     
  
wait:  
    ldr r2, [r1, #NFSTAT_OFFSET]  @ wait ready  
    tst r2, #0x4  
    beq wait  
  
mem_init:  
        /* memory control configuration */  
        /* make r0 relative the current location so that it */  
        /* reads SMRDATA out of FLASH rather than memory ! */  
        ldr     r0, =SMRDATA  
    ldr r1, =mem_init  
        sub     r0, r0, r1  
    adr r3, mem_init       /* r3 <- current position of code   */  
    add r0, r0, r3  
        ldr     r1, =BWSCON     /* Bus Width Status Controller */  
        add     r2, r0, #13*4  
0:  
        ldr     r3, [r0], #4  
        str     r3, [r1], #4  
        cmp     r2, r0  
        bne     0b  
  
    ldr r1, =GPBDAT  
    ldr r2, [r1]  
    bic r2, r2, #(1<<5)    
    str r2, [r1]  
  
        /* everything is fine now */  
        mov     pc, lr  
  
        .ltorg  
/* the literal pools origin */ 

SMRDATA:
    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
    .word 0x32
    .word 0x30
    .word 0x30
